Integrated circuits ("ICs") commonly incorporate one or more fuses, in conjunction with other circuit elements (possibly including more fuses), to control various circuit parameters (i.e. a digital value, a voltage, a current, a gain, a frequency response etc.). In general, a fuse operates in one of two states, namely a "closed" (i.e. low resistance) state, and an "open" (i.e. high resistance) state.
A variety of prior art fuses have been used in ICs. For example, one fuse structure is formed by the so-called "Zener zap" method. Such fuses operate in the "open" state by default, up to the Zener voltage; and are operated in the "closed" state by causing a very large current (typically &gt;200 mA) to flow for a long period of time (typically &gt;1 sec) through the fuse's Zener diode component. The objective is to increase the diode temperature to the point that the metal "spikes" through the junction, thus shorting the Zener diode. "Zener zap" fuses have very low leakage current and very low capacitance when operating in the "open" state at voltages sufficiently lower than the Zener breakdown voltage, both of which are desirable characteristics. Further, only a supply voltage (usually not the IC's own power supply) is needed to "close" such fuses, no extra process steps are required to form such fuses (assuming that Zener diodes are part of the standard process flow employed in fabricating the IC incorporating the fuse), and no extra chip pins are required if probe pads are used.
"Zener zap" fuses are however subject to some significant disadvantages. For example, such fuses can be operated in the "open" state only up to the Zener breakdown voltage. Further, a very large current (typically &gt;200 mA, as aforesaid) must flow through fuse's Zener diode component for a very long time (typically &gt;1 sec) to "close" the fuse. Thus, it may take several seconds to spike the junction as aforesaid. This increases test time and hence cost of the IC. Due to the large currents required, it is usually only possible to spike the junction at probe. Thus, package stress effects on some types of analog circuits can not be trimmed out. A further problem is that the fuse's resistance while operating in the "closed" state can vary widely, depending on factors such as the fabrication process employed, current, metal thickness, crystal orientation, etc. Moreover, the fuse's "open" resistance is voltage-dependent (the closer to the Zener breakdown voltage, the lower the resistance). Additionally, "Zener zap" fuses can of course only be formed by IC fabrication processes having good Zener diode fabrication characteristics.
Another common fuse structure is formed by the so-called "laser fuse link" method. Such fuses operate in the "closed" state by default, and are operated in the "open" state by using a laser to vaporize the fuse link. The link is usually made of a low resistance material such as gatePoly or metal. Desirable characteristics of laser link fuses include their very high "open" resistance (&gt;10M.OMEGA.) if the laser is configured correctly; their low "closed" resistance (typically between 200.OMEGA. to 50 m.OMEGA.); their low capacitance; their usage of only a very small portion of the IC area; the fact that no extra process steps are required to fabricate such fuses; and, the fact that no extra chip pins or probe pads are needed to "open" the fuse (although probe pads or chip pins may be needed to measure the parameter being trimmed).
However, laser link fuses have some disadvantages, including: the need for a laser to "open" the fuse link; possible large variations in "open" resistance if the laser is not properly configured; the fact that there must be no passivation over the link and the resultant reliability hazard if the part is to go into a plastic package; the fact that such fuses can only be "opened" at probe for plastic packages and thus package stress effects on some types of analog circuits can not be trimmed out; and, the fact that it can take up to a full second to align the laser on the link and vaporize it, thus increasing test time and hence cost of the IC.
Another prior art fuse structure is formed by the so-called "poly fuse method #1" method. Such fuses operate in the "closed" state by default, and are operated in the "open" state by applying a high voltage (typically over 10 volts) across the fuse. In more modern fabrication processes this voltage is higher than the breakdown voltage of the devices comprising the IC and hence this voltage is usually forced across the fuse by an external voltage supply via probe pads. However, other probe pads are required to protect the rest of the circuitry from breakdown. Advantages of fuses formed by this method include their low "closed" resistance (typically &lt;500.OMEGA.); the fact that passivation over the poly fuse need not be removed and hence such fuses exhibit better reliability than laser link fuses when encapsulated in plastic packages (however, if the passivation is removed then the voltage needed to "open" the fuse is reduced); the fact that no extra chip pins are required if the fuse is to be "opened" at probe with probe pads; and, their usage of only a small portion of the IC area (typically just the fuse and 2 probe pads).
Fuses formed by the poly fuse method #1 also have short-comings. For example, package stress effects on some types of analog circuits can not be trimmed out if the fuse is "opened" at probe. Further, it is possible that the fuse may "open" only marginally (i.e. exhibit an "open" resistance on the order of about 10 k.OMEGA.). This can happen if the fuse is not "opened" in the correct adiabatic manner by applying the full power of the supply to the fuse and not to its surroundings, resulting in incomplete vaporization. Hence, the sense circuitry must either detect a marginally "open" fuse and attempt to "re-open" it, failing which the part must be discarded; or, apply a much higher voltage across the fuse to ensure correct adiabatic "opening", which in turn necessitates careful protection of circuit devices incapable of withstanding such higher voltages. Since an external voltage source is required, it can take a up to one-half second to "open" the fuse (due to the large parasitic capacitances, the sense point of the supply, etc). This increases test time and hence cost of the IC.
A further problem is that, if a fuse formed by the poly fuse method #1 is not correctly "opened", the fuse may regrow over time (the so-called "poly re-growth" problem), potentially reducing the fuse's "open" resistance to that of a "closed" fuse (the re-growth resistance can be as low as 1 k.OMEGA.). Regrowth is caused by the voltage potential which is inevitably applied across the fuse during normal operation of the circuit; with the regrowth time increasing in inverse proportion to such voltage potential. If digital circuitry is used to sense the fuse, the voltage potential can be quite high, whereas in analog sense circuits the voltage potential in question is highly dependent upon the nature of the circuit.
Yet another prior art fuse structure is formed by the so-called "poly fuse method #2" method (see for example Moyal et al U.S. Pat. Nos. 5,384,727 and 5,412,594). Such fuses operate in the "closed" state by default, and are operated in the "open" state by passing an on-chip current (typically 15 mA) through the fuse via internal circuitry. This requires a fuse having sufficiently low "closed" resistance that the IR drop remains within the maximum supply voltage of the device. Fuses formed by this method usually cannot be placed in the direct analog path (i.e. indrict digital control of the analog parameter being trimmed is required). Advantages of fuses formed by this method include their low "closed" resistance (typically 200.OMEGA.); the fact that passivation over the poly fuse need not be removed and hence such fuses exhibit better reliability than laser link fuses when encapsulated in plastic packages (however, if the passivation is removed then the voltage needed to "open" the fuse is reduced); the fact that no extra chip pins are required if the fuse is to be "opened" at probe; the fact that the fuse can be "opened" either at probe or at package; the fact that the fuse can be measured to determine whether it has been only marginally "opened", and corrective action taken to reopen the fuse (although this requires extra IC area, thus increasing cost of the IC); and, the fact that the fuse can be shorted out by providing extra circuitry to prevent poly re-growth, with the fuse state held by a flip-flop (although this also requires extra IC area and thus increases cost).
The main short comings of fuses formed by the poly fuse method #2 include the fact that if the fuse is "opened" at probe, then package stress effects on some types of analog circuits can not be trimmed out; the fact that the poly fuse may "open" only marginally ("open" resistance on the order of 10 k.OMEGA.); and, the fact that such fuses are subject to the aforementioned "poly re-growth" problem.
Other prior art fuse fabrication techniques requiring special processes have also been developed.
A desirable fuse and fuse fabrication method should:
Be usable either at probe or at package. PA1 Consume no more circuit area than the fuse plus two probe pads. PA1 Provide a mode for simulating fuse "opening" to assess circuit performance without actually "opening" the fuse, thereby simplifying trimming of analog parameters by predetermining the effect of the fuse on such parameters. PA1 Provide a standby mode in which a very small idle current (&lt;1 .mu.A) flows through the fuse, such that at startup the state of the fuse can be determined (i.e. "open" or "closed") and stored, after which the fuse can be operated in standby mode with the aforementioned simulation mode being used to drive the circuit. PA1 Ensure, to a high probability, that the fuse will "open" in the correct adiabatic manner, thereby minimizing the fuse re-growth problem (the standby mode should apply only a very small voltage potential across the fuse to prevent fuse re-growth). PA1 Minimize sense circuitry detection of marginally "open" fuses which exhibit resistance of less than about 5 k. PA1 Facilitate simultaneous "opening" of multiple fuses, thereby reducing test time. PA1 Be implementable in a standard digital CMOS process.
The present invention provides a fuse and fuse fabrication method having the foregoing characteristics.